The present invention relates to electronic devices and, more specifically, to electronic device package structures and methods of fabricating the same.
Electronic devices, such as semiconductor dies, are conventionally enclosed in plastic packages that protect the semiconductor die from hostile environments and that enable electrical interconnection between the semiconductor die and a next level of assembly, such as a printed circuit board (PCB) or motherboard. The elements of a typical electronic package include a conductive leadframe or substrate, an integrated circuit or semiconductor die, conductive structures, such as bond wires or solder balls that electrically connect pads on the semiconductor die to individual leads of the leadframe or substrate; and a hard plastic encapsulant material that covers the other components and forms an exterior of the semiconductor package commonly referred to as the package body. Portions of the individual leads can be exposed for use in electrically connecting the package to the next level assembly.
Consumer electronics devices are continually getting smaller and, with advances in technology, are gaining ever increasing performance and functionality. This is clearly evident in the technology used in consumer electronic products such as smart phones, laptop computers, tablet devices, wearable devices, as well as other electronic devices. Requirements of the smart phone industry, for example, are driving semiconductor packaged components to become smaller with higher functionality and reduced cost. A micro lead frame (MLF) type semiconductor package is one semiconductor package that is capable of realizing such a reduction.
In general, an MLF type semiconductor package is fabricated by forming a lead frame having an adhesion pad and at least one land physically isolated from each other with a resin layer, adhering a semiconductor die to the adhesion pad, connecting the chip pad of the semiconductor die and the land using a conductive wire, and then encapsulating the semiconductor die and the conductive wire with a molding member. Such a process is described in Korean Patent Laid-Open Publication No. 2009-0069884 (published on Jul. 1, 2009).
One problem with prior MLF type semiconductor packages is that the lands became dislodged from the bottom surface of the package during either the manufacturing of the package or subsequently during attachment of the package to a next level of assembly, such as a PCB. This greatly reduced the reliability of MLF type semiconductor packages.
Accordingly, it is desirable to have a structure and method that improve the reliability and functionality of small scale electronic packages such as MLF type semiconductor packages.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures can denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description.